In the ADvanced Super Dimension Switch (AD-SDS, abbreviated as ADS) technology, a parallel electric field generated by fringes of a pixel electrode or a common electrode in the same plane and an electric field generated between the pixel electrode and the common electrode can constitute a multi-dimension electric field, so as to make liquid crystal molecules oriented in all directions between the pixel electrodes or the common electrodes and directly above the electrodes inside a liquid crystal cell capable of rotating, thus improving the operating efficiency of liquid crystals and increasing the light transmittance. The ADS technology can improve the displaying quality of a TFT-LCD, and has advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no push Mura, etc. . .
An ADS display is formed by cell-assembling an ADS array substrate and a color filter substrate, and liquid crystal is injected between the ADS array substrate and the color filter substrate. Generally speaking, as shown in FIG. 1, the ADS array substrate comprises: a substrate 1, and a common electrode layer 8, a gate metal layer 10, a gate insulating layer 12, an active layer 9, a source/drain metal layer 11, an insulating protection layer 7 and a pixel electrode layer 2 sequentially formed on the substrate 1, wherein the gate metal layer comprises the gate electrode and gate lines (not shown in the drawing) of a TFT, the active layer 9 comprises a semiconductor layer 3 and a doping semiconductor layer 4, the source/drain metal layer 11 comprises a source electrode 5, a drain electrode 6 and data lines of the TFT, the pixel electrode layer 2 comprises a pixel electrode, the common electrode layer 8 comprises a common electrode, and the drain electrode 6 of the source/drain metal layer 11 is connected with the pixel electrode layer 2 through a through hole.
Currently, a manufacturing method of the ADS array substrate usually comprises five or even six patterning processes, taking five patterning processes as an example, an implementation process usually comprises: forming the common electrode layer 8 with a first patterning process; forming the gate metal layer 10 with a second patterning process; forming the active layer 9 (the semiconductor layer 3 and the doping semiconductor layer 4) and the source/drain metal layer 11 with a third patterning process; forming the insulating protection layer 7 with a fourth patterning process, and forming the through hole in the insulating protection layer 7 which connects the drain electrode 6 of the source/drain metal layer and the pixel electrode layer 2; forming the pixel electrode layer 2 with a fifth patterning process, thus, the production of the array substrate is completed.
However, as the number of the patterning processes directly affects production cost and yield, and the larger the number of the patterning processes is, the longer the production period is, the higher the production cost is, and the lower the yield is. Therefore, how to effectively reduce the number of the patterning processes is a technical problem that needs to be solved during producing the array substrate.